verilog小程序求救module abc(show_light,rst,clk);input clk;input rst;output[3:0]show_light;reg show;reg aaa;always@(posedge clk)beginif(aaa==0)beginaaa=1;show=0;endelsebeginshow=show+1;endendalways@(posedge rst)beginaaa=0;endassign show_light=sho