请问如下程序是Verilog 还是VHDL语言写的.PARAMETERS(WIDTH = 4,DEPTH = 0);SUBDESIGN altshift(data[(WIDTH - 1)..0] :INPUT;clock :INPUT = GND;aclr :INPUT = GND;clken :INPUT = VCC;result[(WIDTH - 1) ..0] :OUTPUT;)VARIABLEIF DEPTH > 0 GENERATEp

来源：学生作业帮助网编辑：作业帮时间：2024/07/16 20:06:49

x�唿N�P�_�m�'o!)�M��@:T@%4��Wc��eԸ�2"�ޞ�Z0qui{��w��)o��|r;{��O[=�oO��c�EU��>/&��5��hDQ�CIԪ(��vDҀ�,��fQ$�T��a��t �h�]�c9.��}In45�1��AP��,b�c:��9�Yq�U*a�7:7�eW��֛��˶E�5"��?]eQ��D4b�GN�O��\cFH b1ܒp��aA +�'��5��!DRIB��-w�f�r8{r�\&�=��IE�W��덂�u��1��j*IIo��@�'k�E�A6o�Dd�ѳg�IE� �YOލ^G�[�Q�+�^ I��"��Pehg<��=�4Y2��5��nu i��ٍ/+�&S��|�.��w$�݂�8�όl�*xd~>I�

请问如下程序是Verilog 还是VHDL语言写的.PARAMETERS(WIDTH = 4,DEPTH = 0);SUBDESIGN altshift(data[(WIDTH - 1)..0] :INPUT;clock :INPUT = GND;aclr :INPUT = GND;clken :INPUT = VCC;result[(WIDTH - 1) ..0] :OUTPUT;)VARIABLEIF DEPTH > 0 GENERATEp
请问如下程序是Verilog 还是VHDL语言写的.
PARAMETERS
(
WIDTH = 4,
DEPTH = 0
);
SUBDESIGN altshift
(
data[(WIDTH - 1)..0] :INPUT;
clock :INPUT = GND;
aclr :INPUT = GND;
clken :INPUT = VCC;
result[(WIDTH - 1) ..0] :OUTPUT;
)
VARIABLE
IF DEPTH > 0 GENERATE
points[(DEPTH - 1)..0][(WIDTH - 1)..0] :DFFE;
END GENERATE;
BEGIN
IF DEPTH == 0 GENERATE
result[] = data[];
ELSE GENERATE
points[][].clk = clock;
points[][].clrn = aclr;
IF USED(clken) GENERATE
points[][].ena = clken;
END GENERATE;
points[0][].d = data[];
IF DEPTH > 1 GENERATE
FOR row IN 1 TO DEPTH - 1 GENERATE
points[row][].d = points[row - 1][].q;
END GENERATE;
END GENERATE;
result[] = points[DEPTH - 1][].q;
END GENERATE;
IF USED(result) GENERATE
result[] = GND;
END GENERATE;
END;