VHDL问题：can't determine definition of operator ""/""--found 0 possiblelibrary IEEE;use IEEE.STD_LOGIC_1164.all;use IEEE.STD_LOGIC_ARITH.all;use IEEE.STD_LOGIC_UNSIGNED.all;entity frequency isport(clk:in std_logic; frenow:out std_logic_vector

VHDL问题：can't determine definition of operator ""/""--found 0 possiblelibrary IEEE;use IEEE.STD_LOGIC_1164.all;use IEEE.STD_LOGIC_ARITH.all;use IEEE.STD_LOGIC_UNSIGNED.all;entity frequency isport(clk:in std_logic; frenow:out std_logic_vector
VHDL问题：can't determine definition of operator ""/""--found 0 possible
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_ARITH.all;
use IEEE.STD_LOGIC_UNSIGNED.all;
entity frequency is
port(clk:in std_logic;
 frenow:out std_logic_vector(32 downto 0));
end frequency;
architecture BEHAVIORAL of frequency is
begin
process(clk)
variable e:real;
begin
e:=85899*50000000/4294967296;
frenow

VHDL问题：can't determine definition of operator ""/""--found 0 possiblelibrary IEEE;use IEEE.STD_LOGIC_1164.all;use IEEE.STD_LOGIC_ARITH.all;use IEEE.STD_LOGIC_UNSIGNED.all;entity frequency isport(clk:in std_logic; frenow:out std_logic_vector
process(clk)
variable e:integer;
begin
e:=85899*50000000/4294967296;
frenow

/ 在vhdl里好像是求模运算，所以得到的值应该是整数，而你的e定义为real，这样好像是不对的，你将e定义为integer看看。frenow<=e你的这行也不对，frenow是signal类型的，这两种类型不匹配，好像不能赋值。。