protel 99se中pcb进行铺铜之后进行DRC检测后有错误,一、DRC报告如下：PCB File :Documents\PCB1.PCBDate :22-Mar-2011Time :11:08:35Processing Rule :Clearance Constraint (Gap=10mil) (On the board ),(On the board )Violation between Arc (

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protel 99se中pcb进行铺铜之后进行DRC检测后有错误,一、DRC报告如下：PCB File :Documents\PCB1.PCBDate :22-Mar-2011Time :11:08:35Processing Rule :Clearance Constraint (Gap=10mil) (On the board ),(On the board )Violation between Arc (
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protel 99se中pcb进行铺铜之后进行DRC检测后有错误,一、DRC报告如下：PCB File :Documents\PCB1.PCBDate :22-Mar-2011Time :11:08:35Processing Rule :Clearance Constraint (Gap=10mil) (On the board ),(On the board )Violation between Arc (
protel 99se中pcb进行铺铜之后进行DRC检测后有错误,
一、DRC报告如下：
PCB File :Documents\PCB1.PCB
Date :22-Mar-2011
Time :11:08:35
Processing Rule :Clearance Constraint (Gap=10mil) (On the board ),(On the board )
Violation between Arc (2350mil,4850mil) KeepOutLayer and
Polygon Arc (2436.01mil,4851.509mil) TopLayer
Violation between Arc (2350mil,4850mil) KeepOutLayer and
Polygon Arc (2436.009mil,4851.536mil) TopLayer
Violation between Arc (2350mil,150mil) KeepOutLayer and
Polygon Arc (2436.02mil,149.236mil) TopLayer
Violation between Arc (2350mil,150mil) KeepOutLayer and
Polygon Arc (2436.023mil,150mil) TopLayer
Violation between Arc (150mil,4850mil) KeepOutLayer and
Polygon Arc (236.023mil,4850mil) TopLayer
Violation between Arc (150mil,4850mil) KeepOutLayer and
Polygon Arc (236.02mil,4849.236mil) TopLayer
Violation between Arc (150mil,150mil) KeepOutLayer and
Polygon Arc (236.02mil,149.236mil) TopLayer
Violation between Arc (150mil,150mil) KeepOutLayer and
Polygon Arc (236.023mil,150mil) TopLayer
Violation between Arc (2350mil,4850mil) KeepOutLayer and
Polygon Arc (2436.01mil,4851.509mil) BottomLayer
Violation between Arc (2350mil,4850mil) KeepOutLayer and
Polygon Arc (2436.009mil,4851.536mil) BottomLayer
Violation between Arc (2350mil,150mil) KeepOutLayer and
Polygon Arc (2436.02mil,149.236mil) BottomLayer
Violation between Arc (2350mil,150mil) KeepOutLayer and
Polygon Arc (2436.023mil,150mil) BottomLayer
Violation between Arc (150mil,4850mil) KeepOutLayer and
Polygon Arc (236.02mil,4849.236mil) BottomLayer
Violation between Arc (150mil,4850mil) KeepOutLayer and
Polygon Arc (236.023mil,4850mil) BottomLayer
Violation between Arc (150mil,150mil) KeepOutLayer and
Polygon Arc (236.02mil,149.236mil) BottomLayer
Violation between Arc (150mil,150mil) KeepOutLayer and
Polygon Arc (236.023mil,150mil) BottomLayer
Rule Violations :16
Processing Rule :Broken-Net Constraint ( (On the board ) )
Rule Violations :0
Processing Rule :Short-Circuit Constraint (Allowed=Not Allowed) (On the board ),(On the board )
Rule Violations :0
Violations Detected :16
Time Elapsed :00:00:03
二、相关图片
三、我认为错误在禁止布线层也铺上了铜,就是那螺丝孔那.但我不知道如何设置使得在这个圈中不铺铜呢?告诉我如何设置.我开始以为这个禁止布线层那个孔没画完整,不是闭合的圆,我画过一次还是没用.

protel 99se中pcb进行铺铜之后进行DRC检测后有错误,一、DRC报告如下：PCB File :Documents\PCB1.PCBDate :22-Mar-2011Time :11:08:35Processing Rule :Clearance Constraint (Gap=10mil) (On the board ),(On the board )Violation between Arc (
铺铜时把“Remove dead copper”前面打钩试试.
不过螺丝孔不要这样画,可以用place pad,Layer选择Multlayer,设置合适的外半径和孔径.