Error (10334):VHDL error at frame.vhd(6):entity "frame" is used but not delibrary ieee;use ieee.std_logic_1164.all;entity reset is\x05port(clear,frame,sychro:in std_logic;z:out std_logic); end reset; --定义其实体的输入输出端architecture se
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![Error (10334):VHDL error at frame.vhd(6):entity](/uploads/image/z/13568204-20-4.jpg?t=Error+%2810334%29%3AVHDL+error+at+frame.vhd%286%29%3Aentity+%22frame%22+is+used+but+not+delibrary+ieee%3Buse+ieee.std_logic_1164.all%3Bentity+reset+is%5Cx05port%28clear%2Cframe%2Csychro%3Ain+std_logic%3Bz%3Aout+std_logic%29%3B+end+reset%3B+--%E5%AE%9A%E4%B9%89%E5%85%B6%E5%AE%9E%E4%BD%93%E7%9A%84%E8%BE%93%E5%85%A5%E8%BE%93%E5%87%BA%E7%AB%AFarchitecture+se)
Error (10334):VHDL error at frame.vhd(6):entity "frame" is used but not delibrary ieee;use ieee.std_logic_1164.all;entity reset is\x05port(clear,frame,sychro:in std_logic;z:out std_logic); end reset; --定义其实体的输入输出端architecture se
Error (10334):VHDL error at frame.vhd(6):entity "frame" is used but not de
library ieee;
use ieee.std_logic_1164.all;
entity reset is
\x05port(clear,frame,sychro:in std_logic;z:out std_logic);
end reset; --定义其实体的输入输出端
architecture seq of frame is
\x05signal flag:std_logic;
begin
\x05process(clk) --定义一个进行进程,以flag位标志
\x05begin --当flag=1时,提取一次帧同步信息
\x05\x05if falling_edge(clk) then --当flag=0时,不提取帧同步信息
\x05\x05\x05if reset='0' then
\x05\x05\x05\x05flag
Error (10334):VHDL error at frame.vhd(6):entity "frame" is used but not delibrary ieee;use ieee.std_logic_1164.all;entity reset is\x05port(clear,frame,sychro:in std_logic;z:out std_logic); end reset; --定义其实体的输入输出端architecture se
你声明的设计实体名称是reset,那么在结构体声明中也应当采用reset.将“architecture seq of frame is”改为“architecture seq of reset is”.