VHDL library ieee;use ieee.std_logic_1164.all;entity we isport(A,B,C,D:in bit;g,f,e,d,c,b,a:out bit);end we;architecture qwe1 of we issignal comb:bit_vector(3 downto 0);signal temp:bit_vector(6 downto 0);begin combtemptemptemptemptemptemptemptemptemp
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![VHDL library ieee;use ieee.std_logic_1164.all;entity we isport(A,B,C,D:in bit;g,f,e,d,c,b,a:out bit);end we;architecture qwe1 of we issignal comb:bit_vector(3 downto 0);signal temp:bit_vector(6 downto 0);begin combtemptemptemptemptemptemptemptemptemp](/uploads/image/z/13996901-29-1.jpg?t=VHDL+library+ieee%3Buse+ieee.std_logic_1164.all%3Bentity+we+isport%28A%2CB%2CC%2CD%3Ain+bit%3Bg%2Cf%2Ce%2Cd%2Cc%2Cb%2Ca%3Aout+bit%29%3Bend+we%3Barchitecture+qwe1+of+we+issignal+comb%3Abit_vector%283+downto+0%29%3Bsignal+temp%3Abit_vector%286+downto+0%29%3Bbegin+combtemptemptemptemptemptemptemptemptemp)
VHDL library ieee;use ieee.std_logic_1164.all;entity we isport(A,B,C,D:in bit;g,f,e,d,c,b,a:out bit);end we;architecture qwe1 of we issignal comb:bit_vector(3 downto 0);signal temp:bit_vector(6 downto 0);begin combtemptemptemptemptemptemptemptemptemp
VHDL
library ieee;
use ieee.std_logic_1164.all;
entity we is
port(A,B,C,D:in bit;
g,f,e,d,c,b,a:out bit);
end we;
architecture qwe1 of we is
signal comb:bit_vector(3 downto 0);
signal temp:bit_vector(6 downto 0);
begin
combtemptemptemptemptemptemptemptemptemptemptemp
VHDL library ieee;use ieee.std_logic_1164.all;entity we isport(A,B,C,D:in bit;g,f,e,d,c,b,a:out bit);end we;architecture qwe1 of we issignal comb:bit_vector(3 downto 0);signal temp:bit_vector(6 downto 0);begin combtemptemptemptemptemptemptemptemptemp
VHDL不区分大小写,输入端口中的A、B、C、D与输出端口中的a、b、c、d重名了,将输入端口的A、B、C、D改为A_in、B_in、C_in、D_in就可以.