FPGA中用DCM分频问题求助!66分成50的DCM_SP_inst1 :DCM_SPgeneric map (\x05\x05CLKFX_DIVIDE =>10,-- Can be any interger from 1 to 32CLKFX_MULTIPLY =>11)\x05\x05-- Can be any integer from 1 to 32port map (\x05\x05CLKFX => clk3,-- DCM CLK synthe

FPGA中用DCM分频问题求助!66分成50的DCM_SP_inst1 :DCM_SPgeneric map (\x05\x05CLKFX_DIVIDE =>10,-- Can be any interger from 1 to 32CLKFX_MULTIPLY =>11)\x05\x05-- Can be any integer from 1 to 32port map (\x05\x05CLKFX => clk3,-- DCM CLK synthe
FPGA中用DCM分频问题求助!66分成50的
DCM_SP_inst1 :DCM_SP
generic map (
\x05\x05CLKFX_DIVIDE =>10,-- Can be any interger from 1 to 32
CLKFX_MULTIPLY =>11
)\x05\x05-- Can be any integer from 1 to 32
port map (
\x05\x05CLKFX => clk3,-- DCM CLK synthesis out (M/D)
CLKFB => clk4,-- DCM clock feedback
CLKIN => clk1\x05 -- Clock input (from IBUFG,BUFG or DCM)
);
BUFG_inst1 :BUFG
port map (
O => clk4,-- Clock buffer output
I => clk3 -- Clock buffer input
);
我用这个map的时候却总是报错
DCM_SP symbol "DCM_SP_inst1" (output signal=clk3) has an
equation that uses input pin I0,which no longer has a connected signal.
Please ensure that all the pins used in the equation for this LUT have
signals that are not trimmed (see Section 5 of the Map Report File for
details on which signals were trimmed).
这个问题我弄清楚了，请问怎么用FPGA写汉字啊？

FPGA中用DCM分频问题求助!66分成50的DCM_SP_inst1 :DCM_SPgeneric map (\x05\x05CLKFX_DIVIDE =>10,-- Can be any interger from 1 to 32CLKFX_MULTIPLY =>11)\x05\x05-- Can be any integer from 1 to 32port map (\x05\x05CLKFX => clk3,-- DCM CLK synthe
应该做map的时候,发现你的设计里有 的输出信号没有接到任何地方,或者没有输入信号,这部分就会被优化掉,这样导致你的clk4也就没接到任何模块,which no longer has a connected signal.
你看看 Section 5 of the Map Report File,看哪个模块被优化掉了