Error (10170):Verilog HDL syntax error at mpeg2_ts_tb.v(1) near text ";"; expecting a description`timescale 1ps/1ns;module mpeg2_ts_tb;reg clk,clkx2,rstn,sel,send ;reg [15:0] sample_ts[5120000 :0] ;reg [23:0] sample_cnt ;wire [15:0] data_16b ;wire [7

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