英语翻译The VLIW architecture defines a 64-bit instruction bundle.Instructions that are common for computation can be encoded into a three-instruction bundle that issues into scalar execution pipelines.For computationally-intense applications,the
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![英语翻译The VLIW architecture defines a 64-bit instruction bundle.Instructions that are common for computation can be encoded into a three-instruction bundle that issues into scalar execution pipelines.For computationally-intense applications,the](/uploads/image/z/13075386-42-6.jpg?t=%E8%8B%B1%E8%AF%AD%E7%BF%BB%E8%AF%91The+VLIW+architecture+defines+a+64-bit+instruction+bundle.Instructions+that+are+common+for+computation+can+be+encoded+into+a+three-instruction+bundle+that+issues+into+scalar+execution+pipelines.For+computationally-intense+applications%2Cthe)
英语翻译The VLIW architecture defines a 64-bit instruction bundle.Instructions that are common for computation can be encoded into a three-instruction bundle that issues into scalar execution pipelines.For computationally-intense applications,the
英语翻译
The VLIW architecture defines a 64-bit instruction bundle.Instructions that are common for computation can be encoded into a three-instruction bundle that issues into scalar execution pipelines.
For computationally-intense applications,the Tilera compiler generates tight three-instruction per bundle sequences and loops to maximize compute resources and minimize the instruction-stream footprint.
英语翻译The VLIW architecture defines a 64-bit instruction bundle.Instructions that are common for computation can be encoded into a three-instruction bundle that issues into scalar execution pipelines.For computationally-intense applications,the
instruction bundle
指令字符串(或译为:一套指令)