用VHDL编写的计数器,能通过语法检测,但不可以综合,哪里出错了?提示 Variable i :std_logic_vector (7 downto 0) 中的“i” 有以下错误:“Signal i cannot be synthesized,bad synchronous description.The description style yo
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![用VHDL编写的计数器,能通过语法检测,但不可以综合,哪里出错了?提示 Variable i :std_logic_vector (7 downto 0) 中的“i” 有以下错误:“Signal i cannot be synthesized,bad synchronous description.The description style yo](/uploads/image/z/15058090-10-0.jpg?t=%E7%94%A8VHDL%E7%BC%96%E5%86%99%E7%9A%84%E8%AE%A1%E6%95%B0%E5%99%A8%2C%E8%83%BD%E9%80%9A%E8%BF%87%E8%AF%AD%E6%B3%95%E6%A3%80%E6%B5%8B%2C%E4%BD%86%E4%B8%8D%E5%8F%AF%E4%BB%A5%E7%BB%BC%E5%90%88%2C%E5%93%AA%E9%87%8C%E5%87%BA%E9%94%99%E4%BA%86%3F%E6%8F%90%E7%A4%BA+Variable+i+%3Astd_logic_vector+%287+downto+0%29+%E4%B8%AD%E7%9A%84%E2%80%9Ci%E2%80%9D+%E6%9C%89%E4%BB%A5%E4%B8%8B%E9%94%99%E8%AF%AF%EF%BC%9A%E2%80%9CSignal+i+cannot+be+synthesized%2Cbad+synchronous+description.The+description+style+yo)
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