帮忙分析下vHdl程序中(5 DOWNTO 0); 表示什么 怎么来的ARCHITECTURE Behavioral OF FIFO ISTYPE fifo_array IS ARRAY(0 TO 63) OF STD_LOGIC_VECTOR(7DOWNTO 0);—定义长为64宽为8的数组类型 SIGNAL fifo_memory :fifo_array; —定义FIF
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![帮忙分析下vHdl程序中(5 DOWNTO 0); 表示什么 怎么来的ARCHITECTURE Behavioral OF FIFO ISTYPE fifo_array IS ARRAY(0 TO 63) OF STD_LOGIC_VECTOR(7DOWNTO 0);—定义长为64宽为8的数组类型 SIGNAL fifo_memory :fifo_array; —定义FIF](/uploads/image/z/11391334-70-4.jpg?t=%E5%B8%AE%E5%BF%99%E5%88%86%E6%9E%90%E4%B8%8BvHdl%E7%A8%8B%E5%BA%8F%E4%B8%AD%285+DOWNTO+0%29%3B+%E8%A1%A8%E7%A4%BA%E4%BB%80%E4%B9%88+%E6%80%8E%E4%B9%88%E6%9D%A5%E7%9A%84ARCHITECTURE+Behavioral+OF+FIFO+ISTYPE+fifo_array+IS+ARRAY%280+TO+63%29+OF+STD_LOGIC_VECTOR%287DOWNTO+0%29%3B%E2%80%94%E5%AE%9A%E4%B9%89%E9%95%BF%E4%B8%BA64%E5%AE%BD%E4%B8%BA8%E7%9A%84%E6%95%B0%E7%BB%84%E7%B1%BB%E5%9E%8B+SIGNAL+fifo_memory+%3Afifo_array%3B+%E2%80%94%E5%AE%9A%E4%B9%89FIF)
帮忙分析下vHdl程序中(5 DOWNTO 0); 表示什么 怎么来的ARCHITECTURE Behavioral OF FIFO ISTYPE fifo_array IS ARRAY(0 TO 63) OF STD_LOGIC_VECTOR(7DOWNTO 0);—定义长为64宽为8的数组类型 SIGNAL fifo_memory :fifo_array; —定义FIF
帮忙分析下vHdl程序中(5 DOWNTO 0); 表示什么 怎么来的
ARCHITECTURE Behavioral OF FIFO IS
TYPE fifo_array IS ARRAY(0 TO 63) OF STD_LOGIC_VECTOR(7
DOWNTO 0);
—定义长为64宽为8的数组类型
SIGNAL fifo_memory :fifo_array; —定义FIFO的储存介质;
SIGNAL full_flag :STD_LOGIC; —内部满标志信号;
SIGNAL empty_flag :STD_LOGIC; —内部空标志信号
SIGNAL read_addr :STD_LOGIC_VECTOR(5 DOWNTO 0); —读地址
SIGNAL write_addr :STD_LOGIC_VECTOR(5 DOWNTO 0); —写地址
帮忙分析下vHdl程序中(5 DOWNTO 0); 表示什么 怎么来的ARCHITECTURE Behavioral OF FIFO ISTYPE fifo_array IS ARRAY(0 TO 63) OF STD_LOGIC_VECTOR(7DOWNTO 0);—定义长为64宽为8的数组类型 SIGNAL fifo_memory :fifo_array; —定义FIF
SIGNAL write_addr :STD_LOGIC_VECTOR(5 DOWNTO 0);
声明了一组信号,信号名称write_addr,信号类型STD_LOGIC_VECTOR,这个信号的类型是个std_logic数组,它的下标变化范围是(5 DOWNTO 0),也就是说,有6位std_logic类型构成的数组.
说的白一些,就是信号(写地址)write_addr有6根地址线,名称是write_addr(5)~write_addr(0).
信号read_addr也类似.