作业帮求助关于verilog硬件语言的仿真测试向量段module kk(a2,a1,a0,b2,b1,b0,p5,p4,p3,p2,p1,p0 ); input a2,a1module kk(a2,a1,a0,b2,b1,b0,p5,p4,p3,p2,p1,p0 );input a2,a1,a0,b2,b1,b0;output p5,p4,p3,p2,p1,p0;regreg[5:0]result;reg[2:0]a,b;integer
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![求助关于verilog硬件语言的仿真测试向量段module kk(a2,a1,a0,b2,b1,b0,p5,p4,p3,p2,p1,p0 ); input a2,a1module kk(a2,a1,a0,b2,b1,b0,p5,p4,p3,p2,p1,p0 );input a2,a1,a0,b2,b1,b0;output p5,p4,p3,p2,p1,p0;regreg[5:0]result;reg[2:0]a,b;integer](/uploads/image/z/13296949-61-9.jpg?t=%E6%B1%82%E5%8A%A9%E5%85%B3%E4%BA%8Everilog%E7%A1%AC%E4%BB%B6%E8%AF%AD%E8%A8%80%E7%9A%84%E4%BB%BF%E7%9C%9F%E6%B5%8B%E8%AF%95%E5%90%91%E9%87%8F%E6%AE%B5module+kk%28a2%2Ca1%2Ca0%2Cb2%2Cb1%2Cb0%2Cp5%2Cp4%2Cp3%2Cp2%2Cp1%2Cp0+%29%3B+input+a2%2Ca1module+kk%28a2%2Ca1%2Ca0%2Cb2%2Cb1%2Cb0%2Cp5%2Cp4%2Cp3%2Cp2%2Cp1%2Cp0+%29%3Binput+a2%2Ca1%2Ca0%2Cb2%2Cb1%2Cb0%3Boutput+p5%2Cp4%2Cp3%2Cp2%2Cp1%2Cp0%3Bregreg%5B5%3A0%5Dresult%3Breg%5B2%3A0%5Da%2Cb%3Binteger)
求助关于verilog硬件语言的仿真测试向量段module kk(a2,a1,a0,b2,b1,b0,p5,p4,p3,p2,p1,p0 ); input a2,a1module kk(a2,a1,a0,b2,b1,b0,p5,p4,p3,p2,p1,p0 );input a2,a1,a0,b2,b1,b0;output p5,p4,p3,p2,p1,p0;regreg[5:0]result;reg[2:0]a,b;integer
求助关于verilog硬件语言的仿真测试向量段module kk(a2,a1,a0,b2,b1,b0,p5,p4,p3,p2,p1,p0 ); input a2,a1
module kk(a2,a1,a0,b2,b1,b0,p5,p4,p3,p2,p1,p0 );
input a2,a1,a0,b2,b1,b0;
output p5,p4,p3,p2,p1,p0;
reg
reg[5:0]result;
reg[2:0]a,b;
integer bindex;
always@(a2 or a1 or a0 or b2 or b1 or b0)
begin
a={a2,a1,a0};
b={b2,b1,b0};
result=0;
for(bindex=0;bindex<3;bindex=bindex+1)
if(b[bindex])
result=result+(a<<bindex);
{p5,p4,p3,p2,p1,p0}=result;
end
endmodule
仿真向量段?
求助关于verilog硬件语言的仿真测试向量段module kk(a2,a1,a0,b2,b1,b0,p5,p4,p3,p2,p1,p0 ); input a2,a1module kk(a2,a1,a0,b2,b1,b0,p5,p4,p3,p2,p1,p0 );input a2,a1,a0,b2,b1,b0;output p5,p4,p3,p2,p1,p0;regreg[5:0]result;reg[2:0]a,b;integer
首先你的输出没有定义reg这样仿真肯定不过,其次你用for语句不可综合,应该改成
if（bindex==4）
bindex=0;
else
begin
bindex