英语翻译Example 7–52.ASM Update With No Latency(a)LD #6,ASM ; This instruction loads ASM with no; latency.STH A,ASM,*AR1+(b)LD 100h,ASM ; This instruction loads ASM with no; latencyADD A,ASM,B(c)STLM A,ST1 ; This instruction modifies the ASM; f

英语翻译Example 7–52.ASM Update With No Latency(a)LD #6,ASM ; This instruction loads ASM with no; latency.STH A,ASM,*AR1+(b)LD 100h,ASM ; This instruction loads ASM with no; latencyADD A,ASM,B(c)STLM A,ST1 ; This instruction modifies the ASM; f
英语翻译
Example 7–52.ASM Update With No Latency
(a)
LD #6,ASM ; This instruction loads ASM with no
; latency.
STH A,ASM,*AR1+
(b)
LD 100h,ASM ; This instruction loads ASM with no
; latency
ADD A,ASM,B
(c)
STLM A,ST1 ; This instruction modifies the ASM
; field of ST1.No latency is needed
; since STL uses a long offset
; modifier.
STL A,ASM,*+AR5(100h)
Example 7–53.ASM Update With a 1-Cycle Latency
POPM ST1 ; This instruction modifies the ASM
NOP ; field of ST1
SUB A,ASM,B
2677-72 Pipeline SPRU131G
7.5.8 Latencies in Repeat-Block Loops
The following status register fields and bits are affected by latency:
􀀀 BRC (block-repeat counter register)
􀀀 BRAF (block-repeat active flag)
7.5.8.1 Updating Block-Repeat Counter (BRC) Register
A pipeline conflict can occur if two conditions are simultaneously met:
􀀀 An instruction writes to the BRC register
􀀀 The next instruction is an RPTB[D]
The conflict occurs because the second instruction reads BRC in a pipeline
stage that occurs before the previous instruction updates it.
There are certain instructions which do not cause any pipeline conflicts when
updating BRC.Use these instructions wherever possible to avoid conflicts.
Table 7–23.Recommended Instructions for Writing to BRC Before an RPTB Loop
----------------------------------------------------------------
To do this Use thisinstruction -----------------------------------------------------------------
Write an immediate value to BRC STM #lk,BRC
Copy a memory location to BRC MVDK Smem,BRC
----------------------------------------------------------------
Table 7–24 lists latencies between instructions that update BRC and an
RPTB[D] instruction.
Notes:
1) Do not place instructions that modify BRC in the delay slots of a RPTBD
instruction.
2) You are responsible for rearranging instructions or inserting NOPS,if
necessary,to accommodate latencies.
Table 7–24.Latencies for Updating BRC Before an RPTB Loop
First Instruction Latency if Second Instruction Is RPTB[D]
MVDK Smem,BRC
MVMD MMR,BRC 0
STM #k,BRC
ST #k,BRC 0
All other instructions that modify BRC 1
----------------------------------------------------------------
268
麻烦哪位大侠帮忙翻译下,翻译错误一些没关系,但是要和原本的的格式对应一点,看起来漂亮一点就行,重谢

英语翻译Example 7–52.ASM Update With No Latency(a)LD #6,ASM ; This instruction loads ASM with no; latency.STH A,ASM,*AR1+(b)LD 100h,ASM ; This instruction loads ASM with no; latencyADD A,ASM,B(c)STLM A,ST1 ; This instruction modifies the ASM; f
例子7–52.没有潜伏的ASM更新
(a)
LD #6,ASM; 这指示装载ASM没有
; 潜伏.
STH A,ASM,*AR1+
(b)
LD 100h,ASM; 这指示装载ASM没有
; 潜伏
ADD A,ASM,B
(c)
STLM A,ST1; 这指示修改ASM
; ST1的领域.潜伏不是需要的
; 因为STL使用长的垂距
; 修饰词.
STL A,ASM,*+AR5 (100h)
Example 7–53.与1周期潜伏的ASM更新
POPM ST1; 这指示修改ASM
NOP; ST1的领域
SUB A,ASM,B
2677-72管道SPRU131G
7.5.8潜伏在重复阻拦圈
The跟随的状态登记领域,并且位是受潜伏的影响的：
􀀀 BRC (阻拦重复逆记数器)
􀀀 BRAF (阻拦重复活跃旗子)
7.5.8.1更新阻拦重复逆(BRC)记数器 如果二个情况同时符合,A管道冲突可能发生：指示给BRC记数器写的􀀀
􀀀下指示是RPTB [D] 因为第二指示读在管道的BRC The冲突发生 在早先指示之前发生的stage更新它.
There是不导致任何管道冲突,当时的某些指示
updating BRC.在任何可能的情况下使用这些指示避免冲突.
Table 7–23.写的建议使用的指示给在RPTB圈之前的BRC----------------------------------------------------------------
To做这用途thisinstruction -----------------------------------------------------------------
Write对BRC STM #lk,BRC的直接价值
Copy BRC的MVDK Smem,BRC一个存储单元
----------------------------------------------------------------
Table 7–24列出在更新BRC和的指示之间的潜伏RPTB [D]指示.
Notes ：
1)不安置修改在RPTBD的延迟槽孔的BRC的指示
instruction.
2)您负责重新整理指示或插入NOPS,如果
necessary,容纳潜伏.
Table 7–24.更新的BRC潜伏在RPTB圈之前
First指示潜伏,如果第二指示是RPTB [D]
MVDK Smem,BRC
MVMD MMR,BRC 0
STM #k,BRC
ST #k,BRC 0
All修改BRC 1的其他指示