verilog 符号扩展Sign-extending the 24-bit signed (two's complement) immediate to 30 bits.将24位的符号数进行符号扩展成30位的,怎么扩展啊?

来源:学生作业帮助网 编辑:作业帮 时间:2024/07/10 17:07:47
verilog 符号扩展Sign-extending the 24-bit signed (two's complement) immediate to 30 bits.将24位的符号数进行符号扩展成30位的,怎么扩展啊?
x)+K-OWxf:W>8583=O7$5/%3/]$#UD7)D(QR^[WXP`lT]tCɓg@͟/ [cDγ';; Ov$cu#Xb09Tfh)+uyַٴOştYΓ @ldٌ @?jdh`ho!/mgݓVJ4Q$CxC QH/.H̳U@~

verilog 符号扩展Sign-extending the 24-bit signed (two's complement) immediate to 30 bits.将24位的符号数进行符号扩展成30位的,怎么扩展啊?
verilog 符号扩展
Sign-extending the 24-bit signed (two's complement) immediate to 30 bits.将24位的符号数进行符号扩展成30位的,怎么扩展啊?

verilog 符号扩展Sign-extending the 24-bit signed (two's complement) immediate to 30 bits.将24位的符号数进行符号扩展成30位的,怎么扩展啊?
用拼接的方式.
比如,你的a的24bit是a = 24‘b1010_0000_0000_0000_0000_0000
那么符号位拓展的b是b = {6’b11_1111, a}