Error (10500):VHDL syntax error at bijiao.vhd(26) near text "PROCESS"; expecting a sequential statLIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_ARITH.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;ENTITY bijiao ISPORT(A,B:IN BIT_VECTOR(3 DOWNTO 0)
来源:学生作业帮助网 编辑:作业帮 时间:2024/07/08 16:51:29
![Error (10500):VHDL syntax error at bijiao.vhd(26) near text](/uploads/image/z/6361422-6-2.jpg?t=Error+%2810500%29%3AVHDL+syntax+error+at+bijiao.vhd%2826%29+near+text+%22PROCESS%22%3B+expecting+a+sequential+statLIBRARY+IEEE%3BUSE+IEEE.STD_LOGIC_1164.ALL%3BUSE+IEEE.STD_LOGIC_ARITH.ALL%3BUSE+IEEE.STD_LOGIC_UNSIGNED.ALL%3BENTITY+bijiao+ISPORT%28A%2CB%3AIN+BIT_VECTOR%283+DOWNTO+0%29)
Error (10500):VHDL syntax error at bijiao.vhd(26) near text "PROCESS"; expecting a sequential statLIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_ARITH.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;ENTITY bijiao ISPORT(A,B:IN BIT_VECTOR(3 DOWNTO 0)
Error (10500):VHDL syntax error at bijiao.vhd(26) near text "PROCESS"; expecting a sequential stat
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY bijiao IS
PORT(A,B:IN BIT_VECTOR(3 DOWNTO 0);
F1,F2,F3:OUT BIT);
END bijiao;
ARCHITECTURE behave OF bijiao IS
BEGIN
PROCESS(A,B)
BEGIN
IF(A>B) THEN
F1
Error (10500):VHDL syntax error at bijiao.vhd(26) near text "PROCESS"; expecting a sequential statLIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_ARITH.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;ENTITY bijiao ISPORT(A,B:IN BIT_VECTOR(3 DOWNTO 0)
问题是这样子的:
你在第二个分支时使用的是ELSE IF 而不是ELSIF.那么也就是说这个语句中有两个IF语句,你的最后的END IF只是针对最近的IF.所以建议你将第二个分支改成ELSIF就可以了:)