急:vhdl语言编的移位寄存器编译出现错误程序如下:library IEEE;use IEEE.std_logic_1164.all;use IEEE.std_logic_arith.all;use work.cpu_lib.all;entity shift isport ( a :in bit16; sel :in t_shift ; y :out bit16);end shift;architecture
来源:学生作业帮助网 编辑:作业帮 时间:2024/07/29 00:27:19
![急:vhdl语言编的移位寄存器编译出现错误程序如下:library IEEE;use IEEE.std_logic_1164.all;use IEEE.std_logic_arith.all;use work.cpu_lib.all;entity shift isport ( a :in bit16; sel :in t_shift ; y :out bit16);end shift;architecture](/uploads/image/z/11391358-22-8.jpg?t=%E6%80%A5%EF%BC%9Avhdl%E8%AF%AD%E8%A8%80%E7%BC%96%E7%9A%84%E7%A7%BB%E4%BD%8D%E5%AF%84%E5%AD%98%E5%99%A8%E7%BC%96%E8%AF%91%E5%87%BA%E7%8E%B0%E9%94%99%E8%AF%AF%E7%A8%8B%E5%BA%8F%E5%A6%82%E4%B8%8B%EF%BC%9Alibrary+IEEE%3Buse+IEEE.std_logic_1164.all%3Buse+IEEE.std_logic_arith.all%3Buse+work.cpu_lib.all%3Bentity+shift+isport+%28+a+%3Ain+bit16%3B+sel+%3Ain+t_shift+%3B+y+%3Aout+bit16%29%3Bend+shift%3Barchitecture)
急:vhdl语言编的移位寄存器编译出现错误程序如下:library IEEE;use IEEE.std_logic_1164.all;use IEEE.std_logic_arith.all;use work.cpu_lib.all;entity shift isport ( a :in bit16; sel :in t_shift ; y :out bit16);end shift;architecture
急:vhdl语言编的移位寄存器编译出现错误
程序如下:
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use work.cpu_lib.all;
entity shift is
port ( a :in bit16; sel :in t_shift ; y :out bit16);
end shift;
architecture rtl of shift is
begin
shftproc:process(a,sel)
begin
case sel is
when shftpass =>y y y y y y
急:vhdl语言编的移位寄存器编译出现错误程序如下:library IEEE;use IEEE.std_logic_1164.all;use IEEE.std_logic_arith.all;use work.cpu_lib.all;entity shift isport ( a :in bit16; sel :in t_shift ; y :out bit16);end shift;architecture
你的常量前边都没有定义啊
要在前边加上
CONSTANT sftl : std_logic_vector(2 DOWNTO 0) := "000";
同样 sftr等常量也要如上定义